1. Field of the Invention
The present invention relates to a semiconductor device and related operation method. More particularly, the present invention relates to a single-poly electrically erasable programmable read only memory (EEPROM) capable of implementing a rapid edge Fowler-Nordheim erase operation by means of an erase gate thereof and low-voltage data writing through channel hot electron injection (CHEI) mechanism. The single-poly EEPROM according to this invention, which is compatible with standard CMOS fabrication processes, has the advantages of low power consumption, high write/erase efficiency, and high packing density.
2. Description of the Prior Art
Electronic memory comes in a variety of forms to serve a variety of purposes. Flash electrically erasable programmable read only memory (flash EEPROM) is used for easy and fast information storage in such devices as personal digital assistants (PDA), digital cameras and home video game consoles. Generally, an EEPROM chip has a grid of columns and rows with a cell that has two transistors at each intersection. One of the transistors is known as a floating gate, and the other one is the control gate. The floating gate""s only link to the row, or word line, is through the control gate. As long as this link it in place, the cell has a value of 1. Changing the value to a 0 requires a well-known process called Fowler-Nordheim tunneling. It is often desirable to combine many functions on a single device, also called as system-on-a-chip (SOC), to reduce the number and cost of chips. Embedding flash memory in a CMOS device allows a single chip produced by a manufacturer to be configured for a variety of applications, and/or allows a single device to be configured by a user for different applications. To combine with standard CMOS process flow, single-poly flash memory devices have been developed.
FIG. 1 is a schematic, cross-sectional view of a prior art single-poly EEPROM cell 10. As shown in FIG. 1, the EEPROM cell 10 comprises an NMOS structure 28 and a PMOS structure 30. Field oxide layer 24 isolates the PMOS structure 30 from the NMOS structure 28. The NMOS structure 28 is formed on a P-type substrate 12 and comprises an NMOS gate 32, an N+ source region 14, and an N+ drain region 16. The PMOS structure 30 is formed on an N-well 18 and comprises a PMOS floating gate 34, a P+ source region 20, and a P+ drain region 22. A channel stop region 38 is obliquely implanted underneath the PMOS floating gate 34 for facilitating band-to-band hot electron injection into the PMOS floating gate. A conductor 36 directly electrically couples the NMOS gate 32 to the PMOS floating gate 34. That is, there is a conductive current path from one gate to the other, as opposed to indirectly coupling, such as capacitively coupling. Both gates 32 and 34 are floating, that is, they are not directly electrically coupled to a voltage or current source or sink on the IC, and at the same electrical potential. The conductor may be a polysilicon trace formed at the same time as the gates, or may be a metal or silicide conductor formed later in the fabrication sequence.
However, the above described prior art EEPROM cell 10 suffers from several drawbacks. First, the prior art EEPROM cell 10 consumes a lot of chip area since it is composed of a PMOS structure 30 and a NMOS structure 28, and the extra field oxide layer 24 is needed for isolating the PMOS 30 form the NMOS 28. Second, the prior art EEPROM cell 10 needs an extra channel stop region 38 and formation of conductor 36 for connecting two gates, this, in turns, means extra process steps and thus raised cost.
Accordingly, it is a primary object of the claimed invention to provide a high-density single-poly memory device that consumes small per unit chip area. The single-poly memory device according to this invention can be operated under a relatively low voltage and is thus a low power consumption flash memory.
It is another object of the claimed invention to provide a high-density single-poly EEPROM device which is power saving and can be fabricated with conventional CMOS process sequences.
It is still another object of the claimed invention to provide a high-density single-poly EEPROM device and related operation methods.
According to the claimed invention, a single-poly EEPROM is disclosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. An erase gate extending to the floating gate for erasing the single-poly EEPROM is provided in the P-type substrate.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.